VLSI Architectures for Programmable Sorting of Analog Quantities
with Multiple-Chip Support
 
F Ancona, G .Oddone, S Rovetta, G. Uneddu, R. Zunino 
DIBE - Dept. of Biophysical and Electronic Eng. 
University of Genoa 

In: PROOCEEDINGS of the
7th Great Lakes Symposium on VLSI, 1997 

A B S T R A C T 
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The paper describes VLSI architectures for sorting analog quantities. The elementary
circuit unit yields analog representations of sorted values and digitally encodes
the corresponding ranks in the list. The length of the sorted list can be digitally
programmed at run time, hence partial sortings are also supported. The modular, mixed
analog/digital structure is arranged into elementary cells operating at the local
level. This greatly facilitates the layout design and enables multi-chip integration.
A suitable coupling of current-mode and voltage-mode signals minimizes the number
of transistors.